#ifndef __RC2412_TMRB_DEF_H__
#define __RC2412_TMRB_DEF_H__

#ifdef __cplusplus
extern "C"
{
#endif

#define TMRB_LC_Pos                      (0)
#define TMRB_LC_Msk                      (0xfffffffful)
#define TMRB_CV_Pos                      (0)
#define TMRB_LC_Msk                      (0xfffffffful)
#define TMRB_EN_Pos                      (0)
#define TMRB_EN_Msk                      (0x1ul << TMRB_EN_Pos)
#define TMRB_MOD_Pos                     (1)
#define TMRB_MOD_Msk                     (0x1ul << TMRB_MOD_Pos)
#define TMRB_IMK_Pos                     (2)
#define TMRB_IMK_Msk                     (0x1ul << TMRB_IMK_Pos)
#define TMRB_EOI_Pos                     (0)
#define TMRB_EOI_Msk                     (0x1ul << TMRB_EOI_Pos)
#define TMRB_ISR_Pos                     (0)
#define TMRB_ISR_Msk                     (0x1ul << TMRB_ISR_Pos)


#define TMRB_CLK 		    PCLK
#define ONESECOND_COUNT 0x29AAA4      //fpga interrnal clk
#define USER_MODE 		  1
#define FREE_MODE 		  0
#define TMR0            0
#define TMR1            1
#define TMR2            2
#define TMR3            3
#define TMR01_MAX		    0xffffffff    //max time=1583.69s min freq<1Hz
#define TMR23_MAX		    0xffff 		  //max time=0.024s	min freq=42Hz

#define TMRB_ENABLE 	(SYSC->CLK_EN |= TMRB_EN_CLK_Msk)
#define TMRB_DISABLE	(SYSC->CLK_EN &= (~TMRB_EN_CLK_Msk))

#define TMR0_ENABLE     (TMRB->T0CTL |= TMRB_EN_Msk)
#define TMR0_DISABLE    (TMRB->T0CTL &= (~TMRB_EN_Msk))
#define TMR0_USER_MODE  (TMRB->T0CTL |= TMRB_MOD_Msk)
#define TMR0_FREE_MODE  (TMRB->T0CTL &= (~TMRB_MOD_Msk))
#define TMR0_INTR_MASK  (TMRB->T0CTL |= TMRB_IMK_Msk)
#define TMR0_INTR_UNMASK  (TMRB->T0CTL &= (~TMRB_IMK_Msk))
#define TMR0_CLR_INTR   (TMRB->T0EOI)
#define TMR0_GET_CV		(TMRB->T0CV)
#define TMR0_GET_INT_FLAG		(TMRB->T0ISR)
#define TMR0_SEL_INT_CLK 		(SYSC->CLK_SEL &= (~BIT0))
#define TMR0_SEL_EXT_CLK 		(SYSC->CLK_SEL |= BIT0) //external clk from pin GPIO1.12

#define TMR1_ENABLE     (TMRB->T1CTL |= TMRB_EN_Msk)
#define TMR1_DISABLE    (TMRB->T1CTL &= (~TMRB_EN_Msk))
#define TMR1_USER_MODE  (TMRB->T1CTL |= TMRB_MOD_Msk)
#define TMR1_FREE_MODE  (TMRB->T1CTL &= (~TMRB_MOD_Msk))
#define TMR1_INTR_MASK  (TMRB->T1CTL |= TMRB_IMK_Msk)
#define TMR1_INTR_UNMASK  (TMRB->T1CTL &= (~TMRB_IMK_Msk))
#define TMR1_CLR_INTR   (TMRB->T1EOI)
#define TMR1_GET_CV		(TMRB->T1CV)
#define TMR1_GET_INT_FLAG		(TMRB->T1ISR)
#define TMR1_SEL_INT_CLK 		(SYSC->CLK_SEL &= (~BIT1))
#define TMR1_SEL_EXT_CLK 		(SYSC->CLK_SEL |= BIT1) //external clk from pin GPIO1.7

#define TMR2_ENABLE     (TMRB->T2CTL |= TMRB_EN_Msk)
#define TMR2_DISABLE    (TMRB->T2CTL &= (~TMRB_EN_Msk))
#define TMR2_USER_MODE  (TMRB->T2CTL |= TMRB_MOD_Msk)
#define TMR2_FREE_MODE  (TMRB->T2CTL &= (~TMRB_MOD_Msk))
#define TMR2_INTR_MASK  (TMRB->T2CTL |= TMRB_IMK_Msk)
#define TMR2_INTR_UNMASK  (TMRB->T2CTL &= (~TMRB_IMK_Msk))
#define TMR2_CLR_INTR   (TMRB->T2EOI)
#define TMR2_GET_CV		(TMRB->T2CV)
#define TMR2_GET_INT_FLAG		(TMRB->T2ISR)
#define TMR2_SEL_INT_CLK 		(SYSC->CLK_SEL &= (~BIT2))
#define TMR2_SEL_EXT_CLK 		(SYSC->CLK_SEL |= BIT2) //external clk from pin GPIO1.1

#define TMR3_ENABLE     (TMRB->T3CTL |= TMRB_EN_Msk)
#define TMR3_DISABLE    (TMRB->T3CTL &= (~TMRB_EN_Msk))
#define TMR3_USER_MODE  (TMRB->T3CTL |= TMRB_MOD_Msk)
#define TMR3_FREE_MODE  (TMRB->T3CTL &= (~TMRB_MOD_Msk))
#define TMR3_INTR_MASK  (TMRB->T3CTL |= TMRB_IMK_Msk)
#define TMR3_INTR_UNMASK  (TMRB->T3CTL &= (~TMRB_IMK_Msk))
#define TMR3_CLR_INTR   (TMRB->T3EOI)
#define TMR3_GET_CV		(TMRB->T3CV)
#define TMR3_GET_INT_FLAG		(TMRB->T3ISR)
#define TMR3_SEL_INT_CLK 		(SYSC->CLK_SEL &= (~BIT3))
#define TMR3_SEL_EXT_CLK 		(SYSC->CLK_SEL |= BIT3) //external clk from pin GPIO1.9

#define TMRS_CLR_INTR   (TMRBS->TSEOI)


#ifdef __cplusplus
}
#endif
#endif
